1. Field of the Invention
The present invention relates generally to a method and apparatus for accessing a memory device and, in preferred embodiments, a method and apparatus which utilizes an address counter with skipped logic to translate logical addresses to physical addresses to be accessed in a dynamic random access memory (DRAM).
2. Description of Related Art
Volatile storage devices, such as dynamic random access memories (DRAMs), are often used with magnetic storage media to provide buffer memory to temporarily store character information. When other devices, such as non-volatile storage media, access the DRAM, they present logical addresses representing locations in the DRAM where a selected read or write operation will be performed. These logical addresses must be translated to corresponding physical addresses in the DRAM, which are used when performing read/write operations.
Typically, an error checking method is used to detect possible corruption of data stored in the DRAM. One such error checking method involves adding a parity code to each block of data written to the DRAM. This parity code is later used to detect errors in the block of data when it is read out from the DRAM. However, adding a parity code to a block of data in the DRAM complicates the positioning of the data within the DRAM because the parity code interrupts the contiguous storage of data in the DRAM.
Moreover, a system must be provided to map the logical memory address to a physical address in the DRAM. Various methods for translating a logical to a physical address are known in the art, such as the translation methods disclosed in U.S. Pat. No. 5,280,601, entitled "Buffer Memory Control System for a Magnetic Disc Controller," to Dhiru N. Desai et al., assigned to Seagate Technology, Inc., the assignee of the subject application and U.S. Pat. No 5,652,860, entitled "Memory Control Device," to Fumiki Sato, which patents are incorporated by reference herein in their entirety. Prior art translation techniques often involve the use of page tables to map the logical address to the physical address. However, page table techniques often noticeably increase DRAM access time.